Generic port length when integrating existing HDL code with Simulink model using BlackBox

When I integrate existing HDL code with Simulink model (as Black Box), how can I create a component declaration with generic ports length?

For example:

component my_component

generic(GENERIC_OUTPUT_LENGTH: natural := 8)

port (

A, B: in STD_LOGIC;

F : out STD_LOGIC_VECTOR(GENERIC_OUTPUT_LENGTH - 1 downto 0));

end component;

When i use the HDL coder to generate a VHDL code, (GENERIC_OUTPUT_LENGTH - 1 ) is replaced with the specific output port length. However bacuse I use 2 different instantiation (with different ports length) of the same block - the generated code require some correction before it can be synthesized.

Answer 1

[Kiran Kintali]

The problem was reproduced and reported to the development team.

HDL Coder currently supports value generics (generic values that can be specificed and used as gain and constant values). HDL Coder does not support generics to be used to customize input and output types of a VHDL entity or Verilog module.

This limitation pertains to blackbox GenericList parameter and mask parameter as generics feature during HDL Code generation.

We are hoping to enhance the product and address this limtiation in HDL Coder in the upcoming releases.

[Lars Willeboordse]

Hi Kiran,

I'm running into the same issue. Is there by any chance any update on this matter? maybe a timeframe for implementation?

additionally i would like to point out that it seems that passing strings in that same GenericList does not seem to be supported. Simply put it is missing the "" characters after rtl generation.

Best regards lars

[Uday Kumar Gutta]

Hi Lars,

We are actively working in this area; As of now, using generics to specify port length is only supported for RAM instantiations. we would like to connect with you on the usecases. Can you reach out to local support team at MathWorks and connect with us in the development team about next steps?

Thanks

[Bala Naga Kishore]

Hi Kiran,

I am using R2024b version and running into the same issue. Having not able to parameterize the port widths with generics making it hard to instantiate and use pre-written and verified IP multiple times in the same entity.

I am currently solving it by instantiating same IP each time inside a dummy subsystem that would create separate entities and instantiations with fixed port widths in it. Please note that this is still giving Warning during code generation that two different black box systems with same network name have different network interfaces.

Could you please let me know if the option to generate port declarations with generics is available now or if there is any better alternate solution for this issue? Thanks!

Regards,

Kishore

Answer 2

[Kiran Kintali]

Have you used the GenericList parameter in HDLCoder?

Thanks

GenericList

Pass a cell array variable that contains cell arrays each with two or three strings, or enter a cell array of cell arrays that each contain two or three strings. The strings represent the name, value, and optional data type of a VHDL generic or Verilog parameter. The default data type is integer.

Default: none

Specifies a list of VHDL generic or Verilog parameter name-value pairs, each with an optional data type specification, to pass to a subsystem with a BlackBox implementation.

For example, in the HDL Block Properties dialog box, enter {'name','value','type'}, or, if the data type is integer, enter {'name','value'}.

To set GenericList using hdlset_param, at the command line, enter:

hdlset_param (blockname,'GenericList','{''name'',''value'',''type''}');

If the data type is integer, at the command line, enter:

hdlset_param (blockname,'GenericList','{''name'',''value''}');

[evyatar d]

actually i did used it, but it only add a generic parameter, it doesnt change the port length to be with the generic parameter.

[Kiran Kintali]

Can you share a model to describe your usecase? please also attach generated code and expected code with the blackbox settings used in the model.

[Erdinc Atilgan]

Actually, the problem has been stated quite clearly. Despite this, I think the things are made difficult by you. You did not make any effort to create the problem mentioned, dear Kiran. The problem mentioned by evyatar is actually a serious problem. However, as staff, you did not understand the problem, and we will be waiting for a solution. I ran into the same problem and, like evyatar, I wrote a code that fixes the code created by HDL Coder. Could it be a more logical solution for us customers, dear Kiran, to direct the matter to someone who has a better understanding of the subject?

[Kiran Kintali]

Hi Erdinc, If you have already tried the GenericList parameter and it did not meet your requirements, can you reach out to MathWorks tech support for additional support specific to your usecase? Thanks.