Wrap Xilinx IP in Simulink black box

Hi all,

I have done several of the Xilinx tutorials for black-box wrapping of HDL in Simulink but have not come across one yet where more than one HDL file is used. I have a fairly large HDL codebase with ~40 files.

My top file makes use of all the other files (which are contained within pre-defined libraries). I am doubtful as to whether wrapping my top file in a black-box (which I have done) in Simulink, will work. I understand that I could just include all my hdl files in the config.m script, but how would I infer the libraries each set of files belong to?

I have a working Vivado project for this build but asides from that, I am unsure how I need to tell Simulink (and by association system generator) about the hierarchy/libraries/multiple files for correct synthesis and implementation. Do I need to supply accompanying tcl scripts? Is there a way to pass the Vivado project file to System Generator in Simulink? Could I create a custom IP from the Vivado project for wrap that in a black box?

Please assist.

I am happy to share my .slx and config.m (for the black box I have created for my top vhdl file), and Vivado project should you need it.

Thank you.

Using: Vivado 2019.1 and Matlab 2019a.

Talon Myburgh.

Below you can see a screenshot of my black box I've created in Simulink:

Simulink black box of my top HDL file. Block shows in/out ports available and window beside it shows customisable generics. A system generator block is present in the design so that Simulink knows to hand off the design to System Generator in Vivado for Synthesis and Implementation.

Answer 1

[Kiran Kintali]

https://www.mathworks.com/help/hdlcoder/examples/using-xilinx-system-generator-for-dsp-with-hdl-coder.html

Using the Xilinx System Generator Subsystem block enables you to model designs using blocks from both Simulink® and Xilinx, and to automatically generate integrated HDL code. HDL Coder™ generates HDL code from the Simulink blocks, and uses Xilinx System Generator to generate HDL code from the Xilinx System Generator Subsystem blocks.

In the above linked example, the design, or code generation subsystem, contains two parts: one with Simulink native blocks, and one with Xilinx blocks. The Xilinx blocks are grouped into a Xilinx System Generator Subsystem sysgendut that is inside a SLandSysGen Subsystem at the top level of the model hdlcoder_slsysgen. System Generator optimizes these blocks for Xilinx FPGAs. In the rest of the design, Simulink blocks and HDL Coder offer model-based design capabilities and HDL optimizations, such as distributed pipelining and delay balancing.

>> hdlcoder_slsysgen

Recently we have encounted a Xilinx XSG incompatibility that is now resolved here. Please make sure to use the correct bug fix release: https://www.mathworks.com/support/bugreports/2186960

[Talon Myburgh]

Thanks Kiran. This does not address my question (where rather than asking for assistance with generating HDL code, I am asking how to wrap my HDL code in a block for use in Simulink).

Cheers.

Answer 2

[Kiran Kintali]

>> I am asking how to wrap my HDL code in a block for use in Simulink

Hi Talon,

Have you checked this feature which clearly describes how to integrate custom HDL code into a Simulink model using custom code integration appraoch in the overall design generated by HDL Coder.

web(fullfile(docroot, 'hdlcoder/ug/black-box-implementation-for-subsystem-blocks.html'))

web(fullfile(docroot, 'hdlcoder/ug/integrate-custom-hdl-code-using-docblock.html'))

[Talon Myburgh]

Okay thanks. I'll try work with this.

It seems fairly similar to how I mentioned I had already created my black box? I specify a top hdl file for my black box and Simulink generates the ports and things. It does not seem to address how to ensure a set hierarchy of HDL files and libraries are compiled before the top file? From what I have gathered from searching around however, it seems that I can add files to the block by adding them to the config.m file that accompanies a black box in the order they need be compiled?

Also (I don't know if this is owing to my not using the latest version of MATLAB or not), when I right click on a Subsytem block, I do not have the option to make it a BlockBox Implementation. Furthermore, when I right click on a Subsystem block, I don't get the HDL Code option. I'm not sure if doing this is any different to the black box one can drop down from the Xilinx Blockset but just quering all the same.

Thanks.

Talon.

[Kiran Kintali]

>> when I right click on a Subsytem block, I do not have the option to make it a BlockBox Implementation

You need to have a top level Subsystem which is DUT (design under test) that you generate HDL from. Inside the DUT you have regular blocks and subsystems. One or more of those subsystems inside DUT can be marked BlackBox (with a right-click option). Optionally you can embed the BlackBox code within the subsystem itself using a doc block if desired.

Top level DUT cannot be marked blackbox and hence the right-click option is not visible at top level.

[Talon Myburgh]

Understod thanks.

I'll give this all a try.

[SUHANYA M S]

Hi Talon.

I'm trying to do the same thing. I've a Vivado project which inlcudes an IP, 3 modules and 1 top module. One module has 7 sub-modules. The IP is a module, and there's a top module which uses all of these files.

Have you succeeded in including your project with 40 files in Simulink? I see a new component HDL Coder coming up. Should the Black Box in HDL Coder be used to import the HDL wrapper from Vivado, or is it possible to do it with the Blackbox in Xilinx blockset itself?

Please help, I'm kind of stuck here.

[Talon Myburgh]

Hi Suhanya.

Eventually I found the following functionality which you can use within the automatically generated config file black box module creates:

this_block.addFileToLibrary([filepath 'path_to_hdl/module.vhd'],'module_lib');

Note that this functionality only works for hdl source files. I am unable to include .mem files or ip modules.

This can be quite a pain but oh well - also all of this is from this documentation from 2014 and I've not found an update since (this is also the only documentation on this topic).

I myself am not interested in HDL Coder so will continue with this manual way of doing things.