I am trying to generate HDL code for the file attached.
I am trying to make a state machine which takes data at slow data rate and outputs at higher rate with some zero padding too.
Issue arise when I am forced to insert rate transition block at the input port of the state maschine(subsystem1).
when rate transition block is inserted then code is generated which redundent 1 bit registers requirement.
Is there any way to get rid of rate transition block but maintain the fucntionality too.
load mat file before execution.