System Generator: HDL Black Box include mem files.

I have successfully managed to wrap up most of my HDL cores in black boxes in Simulink. They can be successfully simulated and synthesized with System Generator. I've done all this using this user guide.

One block I am having issue wrapping up is a FIR filter for which I have specified window coefficients in .mem files for the BRAM's to load. Now, to add all the VHDL source files the black box needs for compilation/simulation, I used the following commands in the black box configuration MATLAB script (see page 186 of the linked document):

addFile("filename");
addFileToLibrary("filename","library");

These commands successfully add VHDL source files to the Vivado project (in the correct library) that System Generator produces. If I try to include a '.mem' file using the above commands however, it does not add it and synthesis down the line will complain that I do not have the required memory files in my Vivado project (obviously).

No where in that linked document is there mention of how to include memory files so I am reaching out to see whether I am missing something or there is a way in which one ought to overcome this hurdle.

PS. I've asked this question in both the Xilinx Community forum and the Xilinx Reddit page but have received no answer as yet... which is why I am asking here.

Thank you.

Answer 1

[Kiran Kintali]

It looks like it is being addressed here.

https://forums.xilinx.com/t5/AI-Engine-DSP-IP-and-Tools/System-Generator-HDL-Black-Box-include-mem-files/td-p/1233358

[Kiran Kintali]

(add discussion here)

This is because m-script for sysgen does not recognize the .mem files currently. MEM files were introduced with XPM and this support is missing in sysgen. An enhancement request is filed to support this.

This issue can be worked around by adding the absolute path of the mem file in the HDL generic declaration as well as in the m-script as below

GENERIC(
g_adr_w : NATURAL := 9;
g_dat_w : NATURAL := 22;
g_nof_words : NATURAL := 2**9;
g_rd_latency : NATURAL := 2; -- choose 1 or 2
g_init_file : STRING := "C:\sysgenfiles\pfir_coeffs_hanning_t1_p512_b22_wb1_0.mem";
g_ram_primitive : STRING := "auto" --choose auto, distributed, block, ultra
);
 
 
this_block.addGeneric('g_init_file','STRING','"C:\sysgenfiles\pfir_coeffs_hanning_t1_p512_b22_wb1_

When the netlist is generated from Sysgen, the code will refer the mem file in the given path and synthesize fine. Only drawback is if the code is ported to other machine or if the file is moved, the mem file location needs to be provided again.

[Talon Myburgh]

Okay thank you.

Please also be aware that .coe files are also not supported.

Answer 2

[Kiran Kintali]

Are you referring to Xilinx System Generator (XSG) model usecase here? Can you share the model with the issue? What release are you using?

[Talon Myburgh]

Hi yes I am. I'm using Vivado 2019.1 and matlab 2019a.

The model is pretty complex to share as it is a Vivado black box that I've created with quite a bit of accompanying HDL and matlab files. What exactly should I share with you?

[Kiran Kintali]

A sample model that can reproduce the issue would help the team suggest a workaround or address the issue. Thanks

[Talon Myburgh]

Okay that may take a little while but I'll try get something together.

[Talon Myburgh]

Okay, here you go.

In the attached zip folder you will find:

• A simulink design file that holds the Xilinx black box.
• The configuration script for that black box.
• The vhdl code for the module wrapped by the black box.
• The memory initialisation file for the BRAM the vhdl code describes.
• Two images showing Vivado Synthesis results.

If you open the slx and hit 'generate' on System Generator, it will successfully generate a project. If you then open the project in Vivado, it will successfully Synthesize (with a critical warning). The critical warning is shown in VivadoSynthResults_SysGen_produced.png (see attached folder). It appears that despite line 100 of 'ip_xpm_ram_cr_cw_config.m' explicitely adding the memory file to the project, the eventual Vivado project does not contain the memory file for initialisation. If you manually add the memory file to the project, it will compile in Vivado with no further error (see VivadoSynthResults_Edit_addMem.png).

Ultimately, you should gather that the addFile('') command for adding source files in the config script does not allow the adding of .mem, .mif or .coe files.

I hope this is sufficient for you to fix the issue as I require a fix/workaround for the project I'm working on.

Talon.

[Kiran Kintali]

Thanks for the additional info. Waiting to hear from Xilinx team. No update yet.