Domain experts and hardware engineers use MATLAB® and Simulink® to develop prototype and production applications for deployment on Microchip® FPGA and SoC devices.
With MATLAB and Simulink, you can:
- Model hardware architecture at the system level
- Program your FPGA without writing any code
- Simulate and debug your FPGA using MATLAB and Simulink tools
- Perform production FPGA and SoC design
“As a mechatronic systems engineer, my expertise is in control systems and their models, not HDL and FPGAs. With Model-Based Design, I can use my insight and knowledge of the controller and the system being controlled to do more of the work normally done by FPGA engineers and reduce their workload.”Rob Reilink, DEMCON
Using MATLAB with Microchip FPGAs and SoCs
Modeling for FPGA Programming
Add hardware architecture to your algorithm using MATLAB and Simulink. This includes fixed-point quantization, so you can use resources more efficiently, and native floating-point code generation, so you can more easily program FPGAs. Reuse your tests and golden reference algorithm to simulate each successive refinement.
HDL Coder™ generates synthesizable VHDL or Verilog directly from HDL-ready Simulink and MATLAB function blocks for applications such as signal processing, wireless communications, motor and power control, and image/video processing.
Programming Microchip FPGAs and SoCs
HDL Coder guides you through the steps to program your FPGA or SoC directly from Simulink without having to write a single line of code. From HDL Coder, you can optimize and generate synthesizable VHDL® or Verilog® along with AXI interfaces to plug into an SoC. From there you can call Embedded Coder® to generate C/C++ to program the software that runs on the embedded processor. Rather than writing a Verilog testbench or a VHDL testbench, you can also verify your HDL code with MATLAB and Simulink testbenches using HDL cosimulation. Supported simulators include ModelSim™ and Questa™ from Siemens EDA and Cadence® Xcelium®.
Using HDL Coder, you can specify your Microchip FPGA as the target device. You can automatically create a Libero® SoC Design Suite project, perform synthesis, and run place and route.
FPGA Simulation and Debugging
HDL Verifier™ reuses your MATLAB and Simulink test environments to verify your FPGA design.
With cosimulation, you can automatically run your MATLAB or Simulink test bench connected to your Verilog or VHDL design running in a simulator from Mentor Graphics or Cadence Design Systems.
Test your implemented design in your MATLAB or Simulink test bench.
Production FPGA and SoC Design
Domain experts and hardware engineers use MATLAB and Simulink to collaborate on production FPGA and SoC design for wireless, video/image processing, motor/power control, and safety-critical applications.
HDL Coder high-level synthesis optimizations help you meet your design’s goals while maintaining traceability between the generated RTL, the model, and the requirements, which is important for high-integrity workflows such as DO-254. Along with synthesizable VHDL and Verilog, HDL Coder generates IP cores that easily plug into Libero for system integration. HDL Verifier generates verification models that help speed test bench development.