CAEML Research in Hardware Design and Optimization Using Machine Learning

The Center for Advanced Electronics through Machine Learning (CAEML) was established in 2016. Much of its research is starting to bear fruit in real-world applications. We will highlight two Hewlett Packard Enterprise applications that use CAEML research results.

The first is a 56G PAM channel optimization and training speed-up using principal component analysis (PCA) and polynomial chaotic expansion (PCE) surrogate models. A 56G PAM SerDes and a channel with varying loss is measured and machine learning techniques are used to accelerate the channel optimization process and correctly model the SerDes without using any simulations.

The second is a proactive hardware failure prediction method using machine learning techniques developed by CAEML. The method is currently being deployed in the field to proactively remove drives from the field to avoid potential performance degradation and data loss.

The presentation covers:

• A brief introduction of CAEML
• Unique applications of machine learning for hardware design that are different from typical CNN or LSTM neural network applications
• Demonstration of a 56 PAM SerDes performance optimization using PCA and PCE surrogate models
• Production application using proactive hardware failure prediction with casual inference to remove bad drives in the field
• Future investigations of CAEML

CAEML researchers use MATLAB^® and related toolboxes extensively throughout the application development process. For example, the standard MATLAB PCA package was used while custom MATLAB code was developed for the polynomial chaotic expansion surrogate models and the casual inference feature selection functions. The rich mathematical libraries allow rapid development of the prototype special functions.