Introduction to Optimizations in HDL Coder
You use speed and area optimizations in HDL Coder™ to generate HDL code that meets design requirements for speed, area, and throughput. These optimizations do not change the functional behavior of your algorithm, but they can introduce latency or cause differences in sample rates.
Use optimizations when your design does not meet timing, area, or speed requirements. For more information about when to use optimizations during the code generation process, see Basic HDL Code Generation Workflow. To learn how to enable optimizations, see Enabling Optimizations in HDL Coder.
Speed Optimizations
Speed optimizations improve the timing of your design on the target hardware by optimizing the critical path. To identify the critical path more quickly and speed up the iterative process of finding and optimizing the critical path, use critical path estimation. You do not have to run a synthesis or even generate HDL code to generate the critical path estimation report. For more information on performing critical path estimation, see Critical Path Estimation Without Running Synthesis.
Speed optimizations include:
Clock-rate pipelining: An optimization that runs pipeline registers at a faster clock-rate when you specify an oversampling factor greater than one. Use clock-rate pipelining to improve retiming by removing the hierarchical boundaries in a subsystem. This optimization is enabled by default. For more information on setting an oversampling factor, see Oversampling factor and Oversampling. See Clock-Rate Pipelining.
Distributed pipelining: An optimization that retimes existing delays or retimes the registers specified by the InputPipeline and OutputPipeline parameters of specific blocks. To preserve existing delays, disable the Allow design delay distribution setting. To more accurately reflect how components function on hardware and better distribute pipelines and increase clock speed for your target device, use synthesis timing estimates for distributed pipelining. See Use synthesis estimates for distributed pipelining. If you want to retime registers across model hierarchies, enable distributed pipelining on the model. The results of this optimization appear in the Distributed Pipelining section of the optimization report. See Specify Distributed Pipelining Settings.
Adaptive pipelining: An optimization that inserts pipeline registers at the input ports, output ports, or both ports of blocks to create patterns that map blocks to DSP units on the target FPGA device. The optimization considers the target device, target frequency, multiplier word lengths, and the HDL block property settings. The results of this optimization appear in the Adaptive Pipelining section of the optimization report. See Specify Adaptive Pipelining Settings.
Loop unrolling: A MATLAB® optimization that unrolls a loop by instantiating multiple instances of the loop body in the generated code. You can also partially unroll a loop. See Optimize MATLAB Loops.
Area Optimizations
Area optimizations reduce the resource usage of your design. Optimizing your design for area can reduce the speed at which your design runs on the target hardware.
Area optimizations include:
RAM mapping: An optimization that maps large delays, persistent variables in MATLAB code, and pipeline delays to RAM based on a threshold bit width. For more information, see Apply RAM Mapping to Optimize Area, Map pipeline delays to RAM, and RAM mapping threshold.
Resource Sharing: An optimization that identifies multiple functionally equivalent resources and replaces them with a single resource. At the model level, you specify resources you want to share, such as adders and multipliers. At the subsystem level, you use the SharingFactor HDL block property to specify the maximum number of ways to share a single resource. By using the optimization with clock-rate pipelining, you can specify how to overclock the shared resources. For more information, see Resource Sharing.
Streaming: A Simulink® optimization that multiplexes an array data path into a smaller array or scalar data path based on the value of the StreamingFactor HDL block property that you specify on the subsystems. This optimization reduces the hardware resource consumption. For more information, see Streaming.
Loop Streaming: A MATLAB optimization that streams a loop by instantiating the loop body once and using that instance for each loop iteration, depending on the
StreamingFactorproperty that you specify. The code generator oversamples the loop body instance to keep the generated loop functionally equivalent to the original loop. For more information, see Optimize MATLAB Loops.
Benefits and Tradeoffs of Using Speed and Area Optimizations
When you use optimizations in HDL Coder, you optimize for some combination of speed, throughput, area, and power. These optimizations come with tradeoffs which you must consider for your generated HDL code.
HDL Coder optimizations can help you speed up execution times, increase throughput, achieve a smaller design footprint, lower required power consumption, or improve cost efficiency. However, achieving these goals often involves important tradeoffs. When applying speed and area optimizations in HDL Coder, consider the following:
Speed versus Area: Increasing speed often requires more hardware resources, which increases area. Conversely, reducing area may limit how fast the design can run.
Throughput versus Latency: Some optimizations improve throughput at the cost of increased latency.
Sharing Resources versus Maximum Speed: Sharing resources reduces area but can limit the maximum achievable speed if resources become a bottleneck.
Pipeline Stages versus Power Consumption: Adding pipeline stages can increase speed and throughput, but at the cost of increased area and possibly higher power consumption.
Understanding the Impact of Optimizations on Generated HDL Code
HDL Coder provides several optimizations that help you balance speed, area, throughput, and latency. Each optimization has its own set of benefits and costs:
| Optimization | Benefits and Costs | More Information |
|---|---|---|
| Delay Balancing | Benefit: Aligns the signal paths to match the timing and numerics of the generated model with the original model. Cost: Adds extra registers, which increases area and latency. | |
| RAM Mapping | Benefit: Reduces area by mapping large arrays or memories to RAM blocks instead of registers. Cost: May introduce access latency and limit parallel access. | |
| Clock-rate pipelining | Benefit: Automatically inserts pipeline stages to help meet a specified clock-rate. Cost: Increases area and may increase overall latency. | |
| Adaptive Pipelining | Benefit: Achieves higher speed and throughput. Cost: Increases area and latency. | |
| Distributed Pipelining | Benefit: Optimizes placement of pipeline registers for better timing and speed. Cost: May increase area and latency. | |
| Resource Sharing | Benefit: Reduces area and hardware cost. Cost: May lower speed and throughput. and can increase latency if resources become bottlenecks. | |
| Streaming | Benefit: Increases throughput by processing multiple data elements per cycle. Cost: Increases area. | |
| Loop Unrolling | Benefit: Increases parallelism, speed, and throughput. Cost: Increases area usage. |
To understand the impact of optimizations on the generated HDL code:
Review Optimization Reports: You can use the HTML code generation report to evaluate the impact of optimizations on your generated code. For more information on creating and using code generation reports, see Create and Use Code Generation Reports.
Compare Generated and Validation Models: You can visualize the results of the optimizations by generating a Simulink model and comparing the optimized design to the original for functional equivalence. The optimization report contains links to these models. For more information on comparing the original model to the generated model, see Generated Model and Validation Model.
Iterate on Optimizations Settings: You can enable optimizations and adjust the optimization settings at the model, subsystem, or block level. For more information on how to iteratively optimize your design, see Basic HDL Code Generation Workflow. For an example showing how to iterate on the usage of an optimization, see Control the Scope of Delay Balancing.
