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Steve Kuznicki

Last seen: 2 months ago Active since 2015

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Answered
Communication from processor (PS) to the FPGA (PL) via AXI4-lite
You can definitely edit the devicetree file. It's up to you if you want to edit the full file or instead use device tree overla...

4 months ago | 1

Answered
Getting Started with Targeting Xilinx Zynq Platform
This is a documented bug from Xilinx for anyone trying to work with Vivado in the year 2022. We have now released an official p...

4 months ago | 0

Answered
How can I synthesize the Stereo Image Rectification simulink model for Intel Arria?
If you want to target a Zynq device, I would work towards that. There are a few ways that you can create the IP Core and deploy...

1 year ago | 1

| accepted

Answered
How to build a simulink model which can generate HDL coder to resize images or videos?
For HDL code generation - it really depends on if you want resize up or down. If you are using a live video signal (with horizo...

3 years ago | 0

Answered
hw/sw Co-Design Workflow and UDP communication between Zynq zedboard and host computer
You are heading in the right direction here. I think you should consolidate your UDP Send/Recv blocks so there are only one eac...

3 years ago | 1

| accepted

Answered
Pixhawk Video Tutorial with matlab simulink
You will need to become familiar with the PX4 open source flight stack and write your own S-Functions that communicate via the u...

4 years ago | 0

Answered
How can I sovle about external mode problem?
JaeYeong, You will also need to make sure that you are setting the correct serial port parameters in the model. You need to se...

6 years ago | 0

Answered
Pixhawk PX4 to support analog sensor I/O?
Thanks Jones99. We are always looking at ways to improve the support we have for the Pixhawk FMU. For advanced Simulink Us...

7 years ago | 0

Answered
Pixhawk PX4 Support - Vehicle GPS block parameters
Tony, This is the sample time of the block in the Simulink model. This is basically saying that the data will be sampled at 25...

7 years ago | 2

| accepted