ASICs and SoCs
Model, verify, and program your algorithms on ASICs
Domain experts and hardware engineers use MATLAB® and Simulink® to prototype and perform production ASIC design. With MATLAB and Simulink, you can:
- Refine algorithms toward ASIC hardware to eliminate specification miscommunication
- Simulate system-on-chip behavior at a high-level of abstraction
- Begin verification earlier by reusing system-level models and test cases
- Generate production-quality RTL
“The Simulink environment is ideal for system-level architecture exploration. The simulations are 200 times faster than they were in our previous workflow—and Simulink models can be easily converted to C as well as to HDL code, which enables high scalability and reusability.”Ken Chen, Faraday
Using MATLAB with ASICs and SoCs
Modeling for ASIC Design
Add hardware architecture (8:13) to your digital algorithm. This includes fixed-point quantization (30:34), so you can use resources more efficiently, and native floating-point (8:55) code generation, so you can more easily prototype on FPGAs. Reuse your tests and golden reference algorithm to simulate each successive refinement. HDL Coder can generate an HDL test bench that verifies the generated HDL DUT against test vectors saved from your Simulink model.
HDL Coder™ generates synthesizable VHDL or Verilog directly from HDL-ready Simulink and MATLAB function blocks and Stateflow® charts. You can generate code from the same model for early FPGA prototyping (20:51) and production implementation. This approach delivers agility and reuse to your hardware design and verification workflow.
System-on-Chip Behavioral Simulation
Model digital, analog, and software functionality together at a high level of abstraction to identify and eliminate system-level bugs and performance issues before implementation. Simulate memory and internal and external connectivity, as well as scheduling and OS effects, using SoC Blockset™.
Continuously verify your SoC as you refine subsystems, ensuring equivalence and SoC-level compatibility throughout your project.
Begin Verification Earlier
HDL Verifier™ reuses your MATLAB and Simulink test environments to verify your FPGA design.
With cosimulation (5:35), you can automatically run your MATLAB or Simulink test bench connected to your Verilog or VHDL design running in a simulator from Mentor Graphics or Cadence Design Systems.
Export analog or digital models as SystemVerilog DPI (5:19) components for use as reference models, stimulus, or fast simulation models in SystemVerilog simulators from Synopsys, Cadence Design Systems, or Mentor Graphics.
Production ASIC Design
Domain experts and hardware engineers use MATLAB and Simulink to collaborate on production FPGA and SoC design for wireless, video/image processing, motor and power control (24:20), and safety-critical applications.
Explore a broad range of architectural options, then use HDL Coder high-level synthesis optimizations (49:42) to meet your implementation goals. Automatically generate readable RTL that is traceable back to the model and requirements. Along with synthesizable and design rule-compliant RTL, HDL Coder generates a variety of AXI4 interfaces for easy integration into your SoC.