Data Converters

Simulate successive-approximation-register (SAR) and flash analog to digital data converters (ADC)

Simulate and analyze performance metrices of analog to digital data converters. Start from complete system-level models of typical ADC architectures, such as SAR or flash ADC. Modify ADC parameters until you reach your desired system specifications. Use Measurements and Testbenches to validate your design.

Blocks

expand all

Sampling Clock SourceGenerate clock signal with aperture jitter
Flash ADCN-bit ADC with flash architecture
SAR ADCN-bit successive approximation register (SAR) based ADC

Topics

Design and Evaluate a SAR ADC

This example shows how to design a SAR ADC using reference architecture and validate the ADC using ADC Testbench.

Featured Examples