Simulink Blocks Supported for Range Analysis

R2026b

Overview of Simulink Block Support

The following tables summarize range analysis support for Simulink^® blocks. Each table lists all the blocks in each Simulink library and describes support information for that particular block. If the software does not support a given block, where possible, automatic stubbing considers the interface of the unsupported blocks, but not their behavior, during the analysis. However, if any of the unsupported blocks affect the simulation outcome, the analysis may achieve only partial results. If the analysis cannot use automatic stubbing for a block, the block is marked as “not stubbable”. For more information, see Automatic Stubbing.

Not all blocks that are supported for range analysis are supported for fixed-point conversion. To check if a block supports fixed-point data types, see Blocks That Do Not Support Fixed-Point Data Types.

Additional Math and Discrete Library

Simulink Design Verifier™ supports all blocks in the Additional Math and Discrete library.

Commonly Used Blocks Library

The Commonly Used Blocks library includes blocks from other libraries. Unsupported blocks from the Commonly Used Blocks library are listed here under their respective libraries.

Continuous Library

Simulink Design Verifier does not support blocks from the Continuous library except for the Descriptor State-Space block.

Discontinuities Library

Simulink Design Verifier supports all blocks in the Discontinuities library.

Discrete Library

Block	Support Notes
Delay	Supported
Difference	Supported
Discrete Derivative	Supported
Discrete Filter	The software analyzes through the filter. It does not derive any range information for the filter.
Discrete FIR Filter	Supported
Discrete PID Controller	Supported
Discrete PID Controller (2 DOF)	Supported
Discrete State-Space	Not supported
Discrete-Time Integrator	Supported
Discrete Transfer Fcn	Supported
Discrete Zero-Pole	Not supported
Memory	Supported
Tapped Delay	Supported
Transfer Fcn First Order	Supported
Transfer Fcn Lead or Lag	Supported
Transfer Fcn Real Zero	Supported
Unit Delay	Supported
Zero-Order Hold	Supported

Logic and Bit Operations Library

Simulink Design Verifier does not support Logical Operator block when it has more than 100 inputs.

Lookup Tables Library

Simulink Design Verifier does not support these blocks when Interpolation method or Extrapolation method is set to Akima Spline:

• 1-D Lookup Table

• 2-D Lookup Table

• n-D Lookup Table

Math Operations Library

Simulink Design Verifier supports all block from Math Operations library.

Model Verification Library

Simulink Design Verifier supports all blocks in the Model Verification library.

Model-Wide Utilities Library

Simulink Design Verifier does not support Timed-Based Linearization and Trigger-Based Linearization blocks from the Model-Wide Utilities library.

Ports & Subsystems Library

Block	Support Notes
Subsystem, Atomic Subsystem, CodeReuse Subsystem	Supported
Enable	Supported
Enabled Subsystem	Range analysis does not consider the design minimum and maximum values specified for blocks connected to the outport of the subsystem.
Enabled and Triggered Subsystem	Not supported when the trigger control signal specifies a fixed-point data type. Range analysis does not consider the design minimum and maximum values specified for blocks connected to the outport of the subsystem.
For Each	Supported with the following limitations: When For Each Subsystem contains another For Each Subsystem, not supported. When For Each Subsystem contains one or more Simulink Design Verifier Test Condition (Simulink Design Verifier), Test Objective (Simulink Design Verifier), Proof Assumption (Simulink Design Verifier), or Proof Objective (Simulink Design Verifier) blocks, not supported.
For Each Subsystem	Supported with the following limitations: When For Each Subsystem contains another For Each Subsystem, not supported. When For Each Subsystem contains one or more Simulink Design Verifier Test Condition (Simulink Design Verifier), Test Objective (Simulink Design Verifier), Proof Assumption (Simulink Design Verifier), or Proof Objective (Simulink Design Verifier) blocks, not supported.
For Iterator Subsystem	Supported
Function-Call Feedback Latch	Supported
Function-Call Generator	Supported
Function-Call Split	Supported
Function-Call Subsystem	Range analysis does not consider the design minimum and maximum values specified for blocks connected to the outport of the subsystem.
If	Supported
If Action Subsystem	Supported
Inport	—
Model	Supported except for the limitations described in Limitations of Support for Model Blocks.
Outport	Supported
Switch Case	Supported
Switch Case Action Subsystem	Supported
Trigger	Supported
Triggered Subsystem	Not supported when the trigger control signal specifies a fixed-point data type. Range analysis does not consider the design minimum and maximum values specified for blocks connected to the outport of the subsystem.
Variant Subsystem, Variant Model, Variant Assembly Subsystem	Supported
While Iterator Subsystem	Supported

Signal Attributes Library

Simulink Design Verifier supports all blocks in the Signal Attributes library.

Signal Routing Library

Block	Support Notes
Bus Assignment	Supported
Bus Creator	Supported
Bus Selector	Supported
Data Store Memory	When the Data Store Memory variable is tunable, range analysis considers the design ranges specified on the block, and ignores local model writes. When the Data Store Memory variable is not tunable, or Auto, the analysis considers only local model writes. The derived range is the range of the last write to the variable. When the Data Store Memory variable is defined outside of the analyzed system, range analysis uses design ranges.
Data Store Read	Supported
Data Store Write	Supported
Demux	Supported
Environment Controller	Supported
From	Supported
Goto	Supported
Goto Tag Visibility	Supported
Index Vector	Supported
Manual Switch	The Manual Switch block is compatible with the software, but the analysis ignores this block in a model.
Merge	Supported
Multiport Switch	Supported
Mux	Supported
Selector	Supported
Switch	Supported
Vector Concatenate	Supported

Sinks Library

Simulink Design Verifier does not support Record and Stop Simulation blocks from the Sinks library.

Sources Library

Simulink Design Verifier does not support these blocks from the Sources library:

Block	Support Notes
Band-Limited White Noise	Not supported.
Constant	Not supported if Constant value is inf or nan.
From File	Not supported when MAT file data is stored in MATLAB® timeseries format
From Spreadsheet	Not supported.
In Bus Element	Supported if Simulink.Bus type is defined for the In Bus Element block.
Playback	Not supported.
Random Number	Not supported.
Signal Editor	Not supported.
Signal Generator	Not supported if wave form is random.
Uniform Random Number	Not supported.

User-Defined Functions Library

Block	Support Notes
Interpreted MATLAB Function	Not supported
MATLAB Function	The software uses the specified design minimum and maximum values and returned derived minimum and maximum values for instances of variables that correspond to input and output ports. It does not consider intermediate instances of these variables. For example, consider a MATLAB Function block that contains the following code: function y = fcn(u,v) %#codegen y = 2*u; y = y + v; Range analysis considers the design ranges specified for u and v for the instance of y in y = y + v; because this is the instance of y associated with the outport of the block. The analysis does not consider design ranges for the instance of y in y = 2*u; because it is an intermediate instance.
Level-2 MATLAB S-Function	Not supported
S-Function	Not supported
S-Function Builder	Not supported
Simulink Function	Simulink Functions with output arguments that are of complex type are not supported.

Limitations of Support for Model Blocks

Range analysis supports the Model block with the following limitations. The software cannot analyze a model containing one or more Model blocks if:

• The referenced model is protected. Protected referenced models are encoded to obscure their contents. This allows third parties to use the referenced model without being able to view the intellectual property that makes up the model.

  For more information, see Reference Protected Models from Third Parties.

• The parent model or any of the referenced models returns an error when you set the Configuration Parameters > Diagnostics > Connectivity > Element name mismatch parameter to error.

  You can use the Element name mismatch diagnostic along with bus objects so that your model meets the bus element naming requirements imposed by some blocks.

• The Model block uses asynchronous function-call inputs.

• Any of the Model blocks in the model reference hierarchy creates an artificial algebraic loop. If this occurs, take the following steps:

  1. On the Diagnostics pane of the Configuration Parameters dialog box, set the Artificial algebraic loop occurrences not eliminated parameter to error so that Simulink reports an algebraic loop error.

  2. On the Model Referencing Pane of the Configuration Parameters dialog box, select the Minimize artificial algebraic loop occurrences parameter.

     Simulink tries to eliminate the artificial algebraic loop during simulation.

  3. Simulate the model.

  4. Simulink will remove the algebraic loop if possible. If Simulink cannot eliminate the artificial algebraic loop, highlight the location of the algebraic loop by opening the Modeling tab and, in the Compile section, clicking Update Model.

  5. Eliminate the artificial algebraic loop so that the software can analyze the model. Break the loop with Unit Delay blocks so that the execution order is predictable.

  For more information, see Algebraic Loop Concepts.

• The parent model and the referenced model have mismatched data type override settings. The data type override setting of the parent model and its referenced models must be the same, unless the data type override setting of the parent model is Use local settings. You can configure data type override settings to simulate a model that specifies fixed-point data types. Using this setting, the software temporarily overrides data types with floating-point data types during simulation.

  set_param('MyModel','DataTypeOverride','Double')

  For more information, see set_param.

  To observe the true behavior of your model, set the data type override parameter to UseLocalSettings or Off.

  set_param('MyModel','DataTypeOverride','Off')
  

• The referenced model is a Model block with virtual buses at input ports, and the signals in the bus do not all have the same sample time at compilation. To make the model compatible with Simulink Design Verifier analysis, convert the virtual bus to a nonvirtual bus, or specify an explicit sample time for the port.

• When you run the analysis on Model block, then the code generated as a top model is not supported.

• The referenced model is in referenced mode and the model block has periodic event ports enabled. For more information, see Schedule rates with.